The Effect of Dynamic Design Processing for Yield Enhancement in the Fabrication of Deep Sub-Micron MOSFET's

Integrated processing of MOS gate dielectric structures hasbeen carried out in an ultraclean, multichamber processing system as aprototype for cluster (multichamber) processing in order to understandthe potential and limitations of cluster pub 07sm01-rubloff &pubpro-;cessing for this application. With the enhanced surface cleanliness andcontamination control enabled in this process environment, etching of theclean Si surface can occur when very low concentrations of oxygen speciesimpinge on the surface at elevated temperatures, an intrinsic consequenceof Si-0 chemistry. Such etching leads to statistical roughening of theSi surface topography and thereby degrades the electrical properties ofsubsequently fabricated MOS structures. Identification of the etchingreaction leads directly to prescriptions for cluster process integrationwhich prevent etching: (1) ramping up to thermal oxidation temperaturein an ambient with sufficient oxygen concentrations; and/or (2) in-situformation of a passivating oxide surface layer as part of the pre-oxidationcleaning step.